1. Field of Invention
The present invention relates to a prescaling stage for high frequency applications.
2. Description of the Related Art
As it is well known, modern standards for telecommunications (Hyperland 2, DVB-S, SONET) more and more require circuits able to operate at high frequency. In fact, due to the saturation of the range of the frequencies lower than 5 GHz, allocated for applications being now mature and consolidated such as the radiomobile communication system GSM-DCS (Global System for Mobile Communications—Digital Cellular System, previously indicated as GSM-1800) and the UTMS standard (Universal Mobile Telecommunications System), and for being able to support the information transmission at a higher speed and efficiency, the bands C, Ku and K, i.e., the frequencies bands from 4 to 26.5 Ghz, particularly used by telecommunications satellites are currently of main interest.
Moreover, so that the new applications can provide wide commercial diffusion services, it is fundamental that the circuits are realized by means of low cost technologies, and which operate with low supply voltage and with reduced power dissipation.
In these applications, fixed (i.e., non-programmable) frequency prescalers are widely used, being commonly indicated with the term prescalers, employed for frequency scaling the signal generated by oscillators.
In particular, in frequency synthesizers with radio-frequency based on phase locked loops (PLLs), prescalers are used both inside these loops for implementing a first stage of a programmable frequency divider, and at the output of the loops for providing at the output the in phase and in quadrature signal with respect to the divided VCO oscillator signal.
Prescalers are generally digital circuits whose basic stage essentially comprises a divider by-two prescaler. Hereafter in the description indistinct reference will be made to stages or to prescalers. The highest theoretical operation frequency thereof is represented by the transition frequency, fT, of the technology realizing the circuit.
It is also known that bipolar digital circuits in E2CL logic (acronym of the English “Emitter-Emitter Coupled Logic”) succeed in approaching this theoretical limit by using several common collector stages (emitter followers) cascade connected to each other. A driving stage or driver so realized has in fact a high switching speed without being slowed down by the capacitive load of the subsequent stages.
An example of a static frequency prescaling stage 2:1 in E2CL logic is schematically shown in FIG. 1 and globally indicated at 10.
The prescaling stage 10 essentially comprises a bistable circuit, in particular a flip-flop 1 of the D type in turn comprising a master portion 2 and a slave portion 3. In particular, the slave portion 3 of the prescaling stage 10 has an output terminal being inverted-connected to an input terminal of the master portion 2.
Each portion 2, 3 comprises a differential stage 4, 5 for the reading operations and a differential pair 6, 7 of the cross-coupled type for the data holding operations. In particular, the differential stage 4 of the master portion 2 is connected to a supply voltage reference Vcc and it has input terminals connected to respective output terminals of the differential stage 5 of the slave portion 3, in turn connected to supply terminals of the differential pair 7 of such slave portion 3.
In a similar way, the differential stage 5 of the slave portion 3 is connected to the supply voltage reference Vcc and it has input terminals connected to respective output terminals of the differential stage 4 of the master portion 2, in turn connected to supply terminals of the differential pair 6 of such master portion 2.
The master 2 and slave 3 portions also comprise suitable resistive loads RC inserted between the differential stages 4, 5 and the supply voltage reference Vcc.
The master 2 and slave 3 portions also have respective transistor stages 8, 9 connected to the differential stage 4, 5 and to the differential pairs 6, 7 as well as to a second voltage reference, in particular a ground GND, by means of respective current generators G2, G3.
In particular, the transistor stage 8 of the master portion 2 comprises a first Tb1 and a second Tb2 transistors having first conduction terminals connected to the supply voltage reference Vcc by means of the differential stage 4 and the differential pair 6 of the master portion 2, respectively, second common conduction terminals being connected, by means of a first generator G2 of a current IEE to the ground GND, as well as control terminals connected to the differential input terminals IN1 and IN2 of the prescaling stage 10. The control terminals of the first transistor Tb1 of the transistor stage 8 thus corresponds to an input terminal of the master portion 2, while the control terminal of the second transistor Tb2 of the transistor stage 8 corresponds to an output terminal of this master portion 2.
In a similar way, the transistor stage 9 of the slave portion 3 comprises a first Tb3 and a second Tb4 transistors having first conduction terminals being connected to the supply voltage reference Vcc by means of the differential stage 5 and the differential pair 7 of the slave portion 3, respectively, second common conduction terminals being connected, by means of a second generator G3 of a current IEE to the ground GND, as well as control terminals connected to the first input terminal IN1 and to the second input terminal IN2 of the prescaling stage 10, respectively.
The control terminal of the first transistor Tb1 and of the second transistor Tb2 of the transistor stage 8 thus correspond to the input terminals of the slave portion 3. The master 2 and slave 3 stages thus have the same inputs, IN1 and IN2, but they are phase inverted one another. Moreover, as previously described, the output terminal of the slave portion 3 is connected, phase inverted, to the input terminal of the master portion 2.
The prescaling stage 10 also comprises a first T1 and a second T2 output transistors, having first conduction terminals connected to the supply voltage reference Vcc, second conduction terminals connected to a first OUT1 and a second OUT2 output terminals of the prescaling stage 10, respectively, as well as control terminals connected to the output terminal of the differential stage 5 of the slave portion 3 of the flip-flop 1. The output terminals OUT1 and OUT2 of the prescaling stage 10 are also connected to the ground GND, by means of respective current generators Gi1 and Gi2.
The prescaling stage 10 shown in FIG. 1 can be used for low voltage solutions, but it is able to operate at a frequency typically far below the technology transition frequency.
The highest speed of this prescaling stage 10 particularly depends on the cross-coupled differential pairs 6, 7 capacity of correctly carrying out the data holding operation at high frequency.
In particular, considering for simplicity a single cross-coupled differential pair as the one shown in FIG. 2A, it is immediate to verify that the conductance value G(f) thereof has a continuous current (DC) negative value equal to −gm/2 and it grows as the frequency increases.
The quality trend of this conductance is reported by way of example in FIG. 2B.
It is immediate to verify that the conductance becomes positive starting from a frequency given by the following relation:
                              f                      G            =            0                          =                              1                          2              ⁢              π                                ⁢                                                    2                ⁢                π                ⁢                                                                  ⁢                                  f                  T                                                                              r                  B                                ⁢                                  C                  π                                                                                        (        1        )            Cπ and rB being the base-emitter capacitance and the base resistance of the transistors comprised in this pair, respectively.
A differential pair realized in this way thus does not ensure a correct data hold for frequencies higher than fG=O. Moreover, for devices of reduced size, the resistance value rB increases, further decreasing the frequency value fG=O.
For increasing the prescaling stage speed, it is known from the article of H.-M. Rein and M. Möller, “Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s” IEEE J. Solid-State Circuits, Vol. 31, pp. 1076-1090, August 1996, to realize stages which comprise, at the input of the differential pairs, common collector transistors effective to decouple the stages and through which the cross coupling is carried out realizing cross-coupled differential pairs.
A cross-coupled differential pair with common collector stage of this type is schematically shown in FIG. 3A. Substantially, an emitter follower configuration (EF) is inserted in the feedback path of the transistors of the differential pair.
The common connection of the collectors increases the frequency value at which the conductance becomes positive (fG=O), as shown in FIG. 3B by means of the broken line.
In this way it is possible to realize prescalers which operate at high operation frequencies (possibly also close to the theoretical limit fT) by inserting two or more cascade connected common collector stages. Prescalers of this type however cannot be considered of the low-voltage type.
A fixed frequency prescaling stage with common collector stages realized according to the prior art is shown in FIG. 4 and globally indicated with 40. The prescaler stage 40 comprises, with respect to the prescaling stage 10, a first 20 and a second 30 emitter follower stage connected to the master 2 and slave 3 portions, respectively.
In substance, the known solutions have different limits, among which:
1. It is necessary to boost the supply voltage to suitably bias a common collector stage cascade.
2. In common collector stages transistors with wide emitter area have to be used, which requires a high current consumption.
In fact, at high frequencies the current gain of a transistor decreases and thus a single common collector would not be enough to carry out the load decoupling in an efficient way.
Moreover, the output impedance of the common collector stages has a negative real part and it has an inductive behavior which could resonate with the load, which is typically capacitive and thus, potentially, trigger oscillations. Since the negative real part and the inductive behavior of the impedance is linked to the base resistance, rB, of the transistors, the oscillations trigger more easily in the devices of minimum size.
Finally, if in a traditional fixed frequency prescaler it is necessary to boost the supply voltage to operate at frequencies being close to the limit value fT, this implies the need of having devices with wide margin of the breakdown voltage so that they can safely support the high drops of collector-emitter voltage (VCE). Unfortunately, most advanced fast bipolar known technologies generally suffer from a very low breakdown voltage.
These high speed fixed frequency prescalers are thus the critical blocks in the design of circuits for multi-GHz applications, such as for example the new optical fiber networks.